In semiconductor integrated circuit devices, high performance and high logic gate density integration of field-effect transistors are achieved by miniaturization of a gate length following the scaling rule and decreasing a thickness of a gate dielectric film. However, if a gate length of a field-effect transistor becomes equal to or smaller than 30 nanometers, the influence of a short-channel effect should be large, and a cutoff characteristic should be degraded. Therefore, to obtain a favorable cutoff characteristic, there has been proposed a double-gate transistor having fins formed on a silicon-on-insulator (SOI) substrate or on a bulk substrate, having a gate electrode manufactured to cross the fins, and having channels formed at both sides of each fin.
According to such a double-gate transistor, the variation of a threshold voltage is small, the output resistance can be large. If double gate transistors can be installed for the application of a base-band (low frequency) analog devices together with a digital devices, its fabrication cost can be reduced because they are fabricated by almost the same process on the same wafer.
For example, Japanese Patent Application Laid-open No. 2006-269975 discloses a method of reducing a parasitic resistance of fin portions of a fin field-effect transistor (FinFET) and suppressing the variation of the resistance between a source and a channel and between a drain and a channel of the FinFET, by crystal epi-growth of a semiconductor layer connecting between the fin portions, on an upper surface and side surfaces of the fin portions positioned at both sides of a gate electrode.
However, the double-gate transistor has a very small width of fins, has a large parasitic resistance, and has variation of the fin width. Therefore, if a base-band analog circuit is formed with a double-gate transistor with larger parasitic resistance by using a similar design method for a bulk transistor formed on a bulk substrate, sufficient gain cannot be achieved or the characteristic variation of the analog circuit should be degraded.